1. Field of the Invention
The present invention relates generally to a frame alignment circuit and, more specifically, to a frame alignment circuit for a high speed digital transmission.
2. Description of the Prior Art
FIG. 3 show a block diagram of a prior art frame alignment circuit as disclosed in the Japanese laid-open publication No. 2-186850, by Tokkai (1990). In FIG. 3, frame alignment circuit comprises a bit synchronous circuit 1 regenerating a clock pulse from multiplex coded signal. The circuit also includes a line demultiplexing circuit 2, which generates a demultiplex pulse, a low rate demultiplexing line clock pulse, and a synchronous line selecting pulse. These three pulses are generated using the clock pulse which is regenerated in the bit synchronous circuit 1. The frame alignment circuit further includes a decoding circuit 3 for decoding the multiplexed coded signal and forwarding the decoded signal to respective line using the demultiplexed pulse generated in the line demultiplexing circuit 2. The frame alignment circuit has a second AND gate 4 which serves the function of synchronizing the timing between the synchronous line selecting pulse (which is generated by the line demultiplexing circuit 2) and the low rate demultiplexing line clock pulse. The frame alignment circuit further includes a first AND gate 5 which logically multiplies the data of the specified channel of the demultiplexed coded signal by the synchronous line selecting pulse, and a synchronous pattern generator 6, which generates a synchronous pattern using an output of the second AND gate 4. Lastly, the frame alignment circuit includes a mismatch circuit 7 for comparing an output of the AND gate 5 with an output of the synchronous pattern generator 6 to generate a shift pulse if the comparison reveals a mismatch.
FIG. 4 shows a detailed block diagram of the line demultiplexing circuit 2 of the prior art frame alignment circuit. In FIG. 4, the line demultiplexing circuit 2 comprises, D flip-flops 9a-9d. There as many flip-flops as there are multiplexed lines. The flip-flops 9a-9d are connected in cascade fashion. And also included in the circuit is a NOR gate 8 having its input terminals connected to the respected output of the D flip-flop 9a-9c, the output of the NOR gate 8 is connected to a D terminal of the D flip-flop 9a. The circuit 2 also has a demultiplexing line clock generating circuit 10 which generates a line clock by using the output of the D flip-flops 9a-9d. A counter circuit 11 is provided to output a synchronous line selecting pulse showing a position of the frame synchronous pulse by using the demultiplexing pulse generated in the demultiplexing line clock generating circuit 10.
The operation of the above conventional system is explained hereinafter.
In FIG. 3, the multiplexed coded signal is input to the bit synchronous circuit 1. The bit synchronous circuit 1 generates a clock pulse by bit synchronization. The clock pulse passes as input to the line demultiplexing circuit 2, and the line demultiplexing circuit 2 generates the demultiplexing pulse and an accompanying shift pulse. By using the demultiplexing pulse, the decoding circuit 3 converts the multiplexed coded signal to a parallel signal and demultiplexes the multiplexed coded signal to a number of line signal.
As shown in FIG. 4, the line demultiplexing circuit 2 generates the synchronous line selecting pulse (one bit width of the demultiplexing clock pulse) at the position of the frame synchronous pulse by the counter circuit 11. On the other hand, the second AND gate 4 (FIG. 3) synchronizes the synchronous line selecting pulse with the demultiplexing line clock and outputs a pulse to the synchronous pattern generator 6. The synchronous pattern generator 6 generates a synchronous pattern according to the output of the second AND gate 4. On the other hand, a first AND gate 5 logically multiplies the data of the specified channel of the demultiplexed coded signal by the synchronous line selecting pulse. The outputs of the first AND gate 5 and the output of the synchronous pattern generator 6 are compared in the mismatch circuit 7. The mismatch circuit 7 generates a shift pulse having a width of one bit width which is forwarded as input to line demultiplexing circuit 2 if the comparison results indicates a mismatch. When the shift pulse is input to the line demultiplexing circuit 2, the line demultiplexing circuit 2 shifts the demultiplexing pulse by one bit which is output to the decoding circuit 3. This shifting is repeated until the normal frame synchronous bit is at the proper position so that the synchronization is achieved.
In the demultiplexing circuit 2, the one bit shift is executed by applying the shift pulse to the reset terminal R of the D flip-flop 9c. Namely the one bit shift is realized by the shift pulse other than the clock pulse regenerated from the serial multiplexed coded data..
In the prior art frame alignment circuit, as discussed above, when the line numbers n increase, the size of the 1: n line demultiplexing circuit 2 (dividing counter circuit) and the decoder circuit 3 increase. Therefore it becomes burdensome to quickly demultiplex the high rate multiplexed coded signal due to the increased delay time which increases along with to the increasing of the size of the circuit.
It is a primary object of the present invention to provide a frame alignment circuit which demultiplexes the high speed multiplexed coded signal regardless of the number of demultiplexing line.
It is another object of the present invention to provide a frame alignment circuit in which shift operation is realized at a clock rate that is low relative to the rate of multiplexed coded signal.
It is a further object of the present invention to provide a frame alignment circuit having multiplexing circuits, wherein the frame synchronization is easily established by demultiplexing the high rate multi-coding signal even if the demultiplexing line numbers are increased.